The invention relates to an electrically programmable memory cell configuration and a method for fabricating it.
In semiconductor-based electrically programmable memories, so-called EEPROMs, information is stored in the form of at least two different threshold voltages of transistors. In order to read out an item of information of one of the transistors, a voltage lying between the two threshold voltages is applied to a control gate electrode of the transistor. The logic values 0 or 1 are read out depending on whether or not a current flows through the transistor.
The threshold voltage of the transistor can be set by a floating gate electrode, which is electrically insulated and is disposed between the control gate electrode and a channel region of the transistor. To that end, a voltage drop is produced between the control gate electrode and the channel region or a source/drain region of the transistor, which causes electrons to tunnel into or out of the floating gate electrode. A different charge of the floating gate electrode results in different threshold voltages of the transistor.
The name of the floating gate electrode stems from the fact that the electrode is not connected to a potential, i.e. it xe2x80x9cfloatsxe2x80x9d. The name of the control gate electrode stems from the fact that the electrode both controls the programming and serves for reading out the information.
In VLSI technology endeavors are made to increase the packing density of circuit configurations in order to reduce process costs and increase circuit speeds.
In order to avoid short-channel effects in the case of a high packing density, U.S. Pat. No. 5,486,714 proposes an electrically programmable memory cell configuration in which source/drain regions of a transistor which acts as memory cell are disposed on upper parts of two mutually opposite sidewalls of a depression. A channel region of the transistor is U-shaped and runs along the two sidewalls and along a bottom of the depression. A large channel length is obtained by this configuration in the case of a high packing density. A floating gate electrode adjoins four sidewalls and the bottom of the depression. The depression is provided with a thermally grown gate oxide in the region of the channel region. In order to reduce the capacitance formed by the floating gate electrode and the channel region, the gate oxide is somewhat thicker on the two sidewalls of the depression than on the bottom of the depression. When information is erased, electrons tunnel only at the bottom of the depression. Disposed above the floating gate electrode is a control gate electrode, which is isolated from the floating gate electrode by a second dielectric. The control gate electrode is part of a word line running perpendicularly to a connecting line between the source/drain regions. The floating gate electrode overlaps the surface of the substrate outside the depression. One of the source/drain regions is connected to a bit line via a contact. The fact that only a very small read current is available, on account of the in some parts thick gate oxide, is disadvantageous.
A further memory cell configuration is described in U.S. Pat. No. 5,392,237. In this case, the floating gate electrode is likewise disposed in a depression and adjoins four sidewalls of the depression. Insulating structures are disposed on the two sidewalls on which the source/drain regions are not disposed. The gate oxide has a uniform thickness. The source region contains a first part and a second part. The first part is disposed underneath the second part and has a lower dopant concentration than the second part. The first part adjoins the channel region. The first part and the second part adjoin a sidewall of the depression.
U.S. Pat. No. 5,567,635 describes an electrically fen programmable memory cell configuration in which a memory cell contains a MOS-FET, a floating gate electrode and a control gate electrode. The floating gate electrode is disposed on four sidewalls and a bottom of a depression. Two source/drain regions of the MOS-FET adjoin two mutually opposite sidewalls of the depression. Insulating structures adjoin the remaining two sidewalls of the depression. A channel region is disposed at the bottom of the depression. The MOS-FET is a planar transistor. The floating gate electrode is electrically insulated from the MOS-FET by a first dielectric. The first dielectric is thinner on the two sidewalls adjoined by the source/drain regions than on the bottom of the depression. Electrons tunnel only at the two sidewalls of the depression. The floating gate electrode acts as gate electrode of the MOSFET. The control gate electrode is part of a word line running parallel to a connecting line between the two source/drain regions. Japanese Patent JP 1-115164 describes an electrically programmable memory cell configuration in which source/drain regions of a transistor adjoin sidewalls of a depression. The sidewalls and a bottom of the depression are provided with a first dielectric. Adjoining the first dielectric is a floating gate electrode on which a second dielectric and a control gate electrode are disposed. During the writing and art reading of information, electrons tunnel at upper and at lower edges of the depression between the floating gate electrode and the source/drain regions of the transistor.
A coupling ratio is the ratio between a capacitance formed by a control gate electrode and a floating gate electrode and a capacitance formed by the floating gate electrode and a channel region and also source/drain regions of a transistor, that is to say by the floating gate electrode and the substrate. The coupling ratio should be as large as possible in order that tunneling can be triggered even at low operating voltages.
It is accordingly an object of the invention to provide an electrically programmable memory cell configuration and a method for fabricating it which overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, which has a large coupling ratio in comparison with the prior art and can nevertheless be fabricated with a high packing density.
With the foregoing and other objects in view there is provided, in accordance with the invention, an electrically programmable memory cell configuration. The memory cell configuration includes a substrate having a surface and depressions each with a bottom and mutually opposite sidewalls formed therein. A plurality of memory cells having planar it transistors are disposed in the substrate and each of the memory cells has a planar transistor. The planar transistor has two source/drain regions adjoining two of the sidewalls of the depression. A channel region is disposed in the substrate at least part of the bottom of the depression. A first dielectric is disposed on the bottom of the depression in a region of the channel region, the channel region has a cross section that is parallel to the surface of the substrate and intersects the two source/drain regions. A floating gate electrode adjoins the first dielectric and is partially disposed on at least two of the mutually opposite sidewalls of the depression and the depression is constricted but not filled by the floating gate electrode. A second dielectric layer is provided. A control gate electrode is disposed above the floating gate electrode and is insulated from the floating gate electrode by the second dielectric. An insulation layer is disposed on two of the sidewalls of the depression for preventing a capacitance between the two source/drain regions and the floating gate electrode, and parts of the floating gate electrode disposed on the two of the sidewalls of the depression adjoin the insulation layer.
In an electrically programmable memory cell configuration according to the invention, the substrate contains memory cells each having a planar transistor. The channel region of the transistor is disposed in the substrate at at least part of the bottom of the depression that is provided with the first dielectric. The channel region preferably adjoins the entire bottom of the depression. The bottom of the depression is provided with the first dielectric in the region of the channel region. Two source/drain regions of the transistor adjoin the channel region, a cross section through the channel region, the cross section being parallel to the surface of the substrate, intersecting the two source/drain regions. The cross section runs in the vicinity of the bottom of the depression. Parts-of the two source/drain regions are thus disposed at the same level as the channel region. The floating gate electrode of the transistor adjoins the first dielectric and is partially disposed on at least two mutually opposite sidewalls of the depression. The depression is constricted but not filled by the floating gate electrode. The control gate electrode is disposed above the floating gate electrode and is insulated from the floating gate electrode by the second dielectric. The control gate electrode is electrically connected to a word line. The thickness of the first dielectric is dimensioned in such a way that electrons can tunnel through the memory cell during the programming and during the erasure of the memory cell. The source/drain regions adjoin the two sidewalls of the depression. The two source/drain regions thus reach from the surface of the substrate as far as a region of the bottom of the depression. The two sidewalls of the depression are provided with insulation in order to avoid a capacitance formed by the floating gate electrode and the source/drain regions. The thickness of the insulation is dimensioned at least such that, during programming, electrons do not tunnel through the insulation into or out of the floating gate electrode.
A capacitance formed by the control gate electrode and the floating gate electrode is greater than a capacitance formed by the floating gate electrode and the channel region since the floating gate electrode, in contrast to the channel region, is also disposed on at least two sidewalls of the depression. Consequently, an area between the control gate electrode and the floating gate electrode is larger than an area between the channel region and the floating gate electrode. The capacitance between the floating gate electrode and the source/drain regions is negligible. The source/drain regions do not contribute to the coupling ratio.
The coupling ratio is consequently large. Since the enlargement is in the vertical direction, a high packing density can be realized.
In order to simplify the process and in order to increase the packing density, it is advantageous if the control gate electrodes form word lines.
The depression may be produced in the substrate or in a layer in disposed on the substrate. It may also be produced partially in a layer and in the substrate.
The insulation is in spacer form, for example, and may be produced by insulating material being deposited and etched back. The thickness of the insulation is e.g. 30 nm.
In order to make the fabrication as compatible as possible with the fabrication of conventional planar transistors, it is advantageous if the depression is produced in the substrate.
In order to avoid a capacitance formed by the word line and a respective one of the two source/drain regions, the two source/drain regions are preferably disposed in such a way that no connecting line between them is parallel to the course of the word line and the current flow between them runs transversely with respect to the word line. In other words, the word line runs essentially parallel to lines of intersection which are formed by the surface of the substrate and the two sidewalls of the depression. For the same reason, it is advantageous if the word line does not overlap the two source/drain regions i.e. is disposed between the two source/drain regions.
The two source/drain regions may be produced by implantation of the surface of the substrate. As an alternative, a layer grown epitaxially in situ is produced as part of the substrate and patterned. A further possibility is for dopant from a dopant source to diffuse into the substrate.
The depression may be a trench whose length is greater than its width. In this case, a plurality of floating gate electrodes of different transistors are disposed in the trench.
In order to increase the capacitance between the control gate electrode and the floating gate electrode, it is advantageous if the depression is hole-like and has e.g. two further sidewalls that the floating gate electrode likewise adjoins. This enlarges even-more the area between the floating gate electrode and the control gate electrode in comparison with the area between the floating gate electrode and the channel region. The coupling ratio is increased.
In order to prevent a channel current from forming between the source/drain regions of different transistors, the regions being adjacent along the word line, on account of the word line, it is advantageous to dispose first insulating structures between depressions that are adjacent along the word line. In this case, the depression is disposed between two of the first insulating structures that form the two further sidewalls of the depression. The word line overlaps the first insulating structures and a connecting line between the two first insulating structures runs parallel to it.
The first insulating structures may be produced for example by trenches that run essentially parallel to one another being produced before the depression is produced, the trenches being filled with insulating material. The first insulating structures fill the trenches. The depressions can then be produced between the trenches by masked etching. In order to ensure that the two further sidewalls of the depression are formed by the first insulating structures, it is advantageous if a strip-type mask is used during the masked etching, the strips of which mask run transversely with respect to the trenches. As an alternative, the mask does not cover only those regions of the substrate in which the depressions are produced.
Another possibility for producing the first insulating structures is to produce the depressions by partial removal of the insulating material in the trenches. The first insulating structures are in the form of pillars in this case.
The floating gate electrode is produced by patterning of a conductive first layer that constricts, but does not fill, the depression.
It is advantageous if the floating gate electrode does not project appreciably from the depression. In this case, in order to pattern the conductive first layer, the conductive first layer may be planarized until parts of the conductive first layer which are situated outside the depression have been removed. In this way, a mask is not required for producing the floating gate electrode, which simplifies the process. In order to planarize the conductive first layer, planarization material may be deposited, which is planarized at the same time as the conductive first layer. After the parts of the conductive first layer that are situated outside the depression have been removed, remaining planarization material can be removed.
In order to avoid short-channel effects, it is advantageous if the two source/drain regions each contain a first part and a second part adjoining the latter. First parts of the two source/drain regions are each disposed on one of the two sidewalls of the depression and such that they adjoin the channel region, and have a lower dopant concentration than second parts of the source/drain regions which adjoin neither the sidewalls of the depression nor the channel region.
The second parts of the source/drain regions may be produced by implantation with the aid of a mask. In order to simplify the process, it is advantageous if the mask contains the word line and adjoining spacers along the word line. The spacers can be produced without a high outlay by material being deposited and etched back after the word line has been produced.
The spacers can be removed or left. If the spacers are left, then it is advantageous if the spacers are produced from insulating material, since a capacitance between the word line and the two source/drain regions is avoided as a result of this.
In order to make the fabrication as compatible as possible with the fabrication of conventional planar transistors, it is advantageous if the first parts of the two source/drain regions are produced by implantation, the word line serving as a mask. In this case, the spacers are not produced until after the first parts of the two source/drain regions have been produced.
The first parts of the source/drain regions may also be produced before the depression is produced. By way of example, they are produced from a doped layer of the substrate that is patterned by the depression and the first insulating structures.
A bit line runs transversely with respect to the word line. Transistors that are adjacent along the bit line may be connected in series (NAND architecture) or in parallel (NOR architecture). If the transistors are connected in series, then they form the bit line. If the transistors are connected in parallel with one another, then a source/drain region of the transistors is in each case connected to the bit line. The connection is effected via a contact, for example.
In both cases, it is advantageous for the purpose of increasing the packing density if two of the transistors which are adjacent to one another along the bit line in each case have a common source/drain region.
It is advantageous if a periphery of the memory cell configuration that contains the planar transistors and/or planar high-voltage transistors is disposed in the substrate.
High-voltage transistors are operated with high voltages, e.g. 18 volts, and require large channel lengths. The high-voltage transistors switch e.g. programming voltages that are higher than the read voltage. They serve for the writing or erasure of the memory cells.
In order to simplify the process, it is advantageous if the planar transistors and the planar high-voltage transistors of the periphery are produced at the same time as the transistors of the memory cells.
With the foregoing and other objects in view there is further provided, in accordance with the invention, a method for fabricating an electrically programmable memory cell configuration, which includes providing a substrate. A depression having a bottom and sidewalls is produced in the substrate. A first dielectric is disposed at least partially at the bottom of the depression. A channel region of a planar transistor of a memory cell is produced in the substrate, the channel region adjoins the first dielectric. Two source/drain regions of the planar transistor are formed by implantation of a surface of the substrate such that the two source/drain regions adjoin two mutually opposite sidewalls of the depression. A cross section through the channel region is parallel to the surface of the substrate, and intersects the two source/drain regions. An insulation is applied to the two mutually opposite sidewalls of the depression. A conductive layer is applied to the depression resulting in the depression being constricted, but not filled, by the conductive layer. The conductive layer is then patterned thus forming a floating gate electrode of the planar transistor. The floating gate electrode adjoins the first dielectric and the insulation, the insulation prevents a formation of a capacitance between the floating gate electrode and the two source/drain regions. A second dielectric layer is formed above the floating gate electrode, and a control gate electrode is formed above the second dielectric layer.
By way of example, the first insulating structures may be produced together with second insulating structures of the transistors of the periphery and with third insulating structures of the high-voltage transistors of the periphery.
The second insulating structures each surround one of the transistors of the periphery. The third insulating structures each surround one of the high-voltage transistors of the periphery.
Furthermore, after the production of a gate dielectric of the transistor of the periphery and of a gate dielectric of the high-voltage transistor of the periphery, a second layer may be applied and patterned, thereby simultaneously producing the control gate electrode as part of the word line, a gate electrode of the transistor of the periphery and a gate electrode of the high-voltage transistor of the periphery.
The first parts of the two source/drain regions of the of the memory cell, first parts of source/drain regions of the transistor of the periphery and first parts of source/drain regions of the high-voltage transistor of the periphery can be produced simultaneously by implantation, the word line, the gate electrode of the transistor of the periphery and the gate electrode of the high-voltage transistor of the periphery acting as masks, as is customary in the conventional method for producing planar transistors. All first parts of the source/drain regions are doped more weakly than second parts of the source/drain regions. The first parts adjoin associated channel regions, as a result of which short-channel effects are suppressed.
The second parts of the two source/drain regions of the transistor of the memory cell, second parts of the source/drain regions of the transistor of the periphery and second parts of the source/drain regions of the high-voltage transistor of the periphery can be produced simultaneously. The spacers and further spacers which are produced at the same time as the spacers on sidewalls of the gate electrode of the transistor of the periphery and of the gate electrode of the high-voltage transistor of the periphery acting as a mask.
Since short-channel effects are particularly critical in the case of the high-voltage transistor, it is advantageous to use here an e.g. web-type mask which covers the gate electrode of the high-voltage transistor, the associated spacers and a surrounding region-so that the first parts of the source/drain regions of the high-voltage transistor are made particularly large.
The transistor of the memory cell, the transistor of the periphery and the high-voltage transistor of the periphery may be n-channel or p-channel transistors.
In accordance with an added feature of the invention, a connecting line is produced between the two source/drain regions. A word line is produced such that it is electrically connected to the control gate electrode and that the connecting line between the two source/drain regions is not parallel to a course of the word line.
In accordance with an additional feature of the invention, first insulating structures are produced in the substrate. The depression is then formed between two of the first insulating structures. The first insulating structures form two of the sidewalls of the depression, and the floating gate electrode is patterned such that it also adjoins the first insulating structures and thus at least four of the sidewalls of the depression.
In accordance with another feature of the invention, after the conductive layer has been applied, a planarization material is deposited and planarized until parts of the conductive layer situated outside the depression are uncovered. The planarization of the parts of the conductive layer situated outside of the depression continues until the parts are removed, the floating gate electrode which does not project out from the depression thereby being produced.
In accordance with another added feature of the invention, a first part of each of the two source/drain regions is produced. The first part adjoins one of the two mutually opposite sidewalls of the depression and the channel region. After the word line has been produced, a material is deposited and etched back for producing spacers along sidewalls of the word line. A second part of each of the two source/drain regions is produced by implantation with an aid of the spacers being used as a mask, the second part being doped more heavily than the first part and adjoins the first part.
In accordance with another additional feature of the invention, the planar transistor is one of a plurality of planar transistors-produced in a plurality of depressions, and each two of the planar transistors which are adjacent to one another transversely with respect to the word line share a common source/drain region. A bit line is formed by series-connecting the planar transistors that are adjacent to one another transversely with respect to the word line.
In accordance with a further feature of the invention, the planar transistor is one of a plurality of transistors produced in a plurality of depressions, and each two of the planar transistors which are adjacent to one another transversely with respect to the word line share a common source/drain region. A bit line is produced connected to a respective source/drain regions of each of the planar transistors which are adjacent to one another transversely with respect to the word line.
In accordance with a concomitant feature of the invention, at least one second insulating structure of a further planar transistor of a periphery of the memory cell configuration and a third insulating structure of a planar high-voltage transistor of the periphery are produced in the substrate together with the first insulating structures. Before the control gate electrode is produced, a gate dielectric of the further planar transistor of the periphery and a gate dielectric of the planar high-voltage transistor of the periphery are produced. A further layer is applied and patterned thereby producing the control gate electrode that is part of a word line, a gate electrode of the further planar transistor of the periphery and a gate electrode of the planar high-voltage transistor of the periphery. First parts of the two source/drain regions of the planar transistor of the memory cell, first parts of source/drain regions of the further planar transistor of the periphery, and first parts of source/ drain regions of the planar high-voltage transistor of the periphery are produced by implantation. The word line, the gate electrode of the further planar transistor of the periphery and the gate electrode of the planar high-voltage transistor of the periphery act as masks. A material for producing spacers along sidewalls of the word line is deposited and etched back. Further spacers are formed on sidewalls of the gate electrode of the further planar transistor of the periphery. Finally, second parts of the two source/drain regions of the planar transistor of the memory cell, second parts of the source/drain regions of the further planar transistor of the periphery and second parts of the source/drain regions of the planar high-voltage transistor of the periphery are produced, where at least the spacers and the further spacers act as a mask.
One possible method of operation of the electrically programmable memory cells according to the invention is described below.
In the case of the NOR architecture, in order to write the logic value xe2x80x9c1xe2x80x9d to a transistor, the associated word line is connected to a voltage of xe2x88x9212 volts and the associated bit line is connected to a voltage of 5 volts. The remaining word lines and the remaining bit lines are at 0 volts. On account of the voltage drop between the word line, i.e. the control gate electrode of the transistor, and the bit line, i.e. a source/drain region of the transistor, electrons tunnel through the first dielectric from the floating gate electrode into the source/drain region. During erasure, a voltage of 0 volts is present on the bit line, while the word line is connected to 17 volts, with the result that electrons can tunnel from the channel region into the floating gate electrode. This corresponds to the logic value 0.
In the case of the NAND architecture, the transistor is programmed by a voltage of 17 volts being applied to the word line, while the bit line remains at 0 volts. To ensure that transistors which are adjacent along the word line are not likewise programmed, the adjacent bit lines can be connected to a voltage of approximately 8 volts. Erasure can be effected by the word lines being connected to 0 volts, while the channel region is connected to approximately 16 volts via the well.
In order to read out the information of the transistor, in the case of the NOR architecture, the associated word line is connected to a voltage of approximately 2.5 volts which lies between the two possible threshold voltages of the transistor, corresponding to the logic values 0 or 1. By the bit line, an evaluation is made as to whether or not a current flows through the transistor.
In the case of the NAND architecture, in order to read out the ES information of the transistor, the word line is connected to approximately 2.5 volts, while the remaining word lines are connected to approximately 5 volts.
An evaluation is then made as to whether or not a current flows in the case of approximately 5 volts on the bit line.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an electrically programmable memory cell configuration and a method for fabricating it, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.